Generally, semiconductor memory devices may be classified into a volatile memory devices and non-volatile memory devices. Volatile memory devices may include, for example, dynamic random access memory (DRAM) devices and static random access memory (SRAM) device, among others and may lose data over time. Non-volatile memory devices may continuously store data for significant periods of time. Non-volatile memory devices may include an electrically erasable programmable read only memory (EEPROM), a flash memory device, among others, and may be capable of electrically inputting/outputting data. Flash memory devices may include progressive types of EEPROM that may be capable of rapidly erasing data. Flash memory devices may electrically control input/output of data using Fowler-Nordheim (F-N) tunneling or hot electrons.
Flash memory devices may be classified into NAND type flash memory devices and NOR type flash memory devices. The NOR type flash memory devices may provide for rapid operation. In contrast, the NAND type flash memory devices may be more readily integrated.
The NAND flash memory devices may use rapid programming and erasing at a relatively low voltage. To achieve the rapid programming and erasing at a relatively low voltage, it may be beneficial to provide each of unit cells in the NAND type flash memory device with a high coupling ratio.
In order to increase the coupling ratio, a high capacitance may be provided between a floating gate pattern and a control gate pattern in the cell. In contrast, a low capacitance may be provided between the floating gate pattern and a semiconductor substrate.
The high capacitance between the floating gate pattern and the control gate pattern may be provided by using a metal oxide having a high dielectric constant for a dielectric layer. When the dielectric layer includes the metal oxide having the high dielectric constant, a sufficient capacitance may be provided without increasing of an effective surface area of the floating gate pattern. In this regard, the floating gate pattern may be thin by forming the dielectric layer only on an upper surface of the floating gate pattern and not on a sidewall of the floating gate pattern.
Further, when the floating gate pattern is thin, interference between the adjacent floating gate patterns may be reduced. Therefore, distribution of threshold voltages between the cells caused by the interference may also be decreased.
However, when the dielectric layer is formed using the material having a high dielectric constant, charges in the floating gate pattern may be partially discharged due to the dielectric layer. Particularly, a plurality of trap sites may exist in the dielectric layer having the high dielectric constant. Accordingly, the charges in the floating gate pattern may escape through the trap in the dielectric layer via an electric field between the floating gate pattern and the control gate pattern and thus the charges in the floating gate pattern may be partially lost. The partial loss of the charges in the floating gate pattern may result in changes and/or loss of the data and malfunctions of the NAND type flash memory devices. As a result, the NAND type memory devices may have low reliability.
Therefore, a non-volatile memory device that is formed using the material having a high dielectric constant and that provides stable functionality and good reliability may be desired. Further, methods of operating the non-volatile memory device that may avoid the malfunctions and improve the reliability, may also be desired.